Rohan Katiyar
Broadcom
- Role
- Senior Design Engineer at Broadcom
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Rohan Katiyar
5+ years of experience in custom layout, memory layout, standard cell layout and physical verification in technologies like 12 nm, 16 nm, 14nm, 22 nm, 40 nm.• Expertise in full chip physical verification (DRC, LVS), electrical checks (ERC), reliability analysis (sigEM, powerEM, IR.)• Expertise in Cadence Virtuoso and Custom Compiler for layout design• Expertise in Mentor Graphics Calibre and IC Validator for physical verification.• Expertise in Virtuoso Layout XL for optimized floorplanning and routing.• Working knowledge on 3D FinFET TSMC16nm, TSMC 7nm, SMIC12 nm.• Knowledge of various layout dependent effects like Antenna violation, EM violation, Latch-up, IR drop, WPE.• Major contribution in very successful projects (Soc chip with 10Ghz processor) at RealSilicon.• Capable of working in a cross functional, multi site team environment spread across various geographies and time zones.• Capable of guiding junior layout designers with project deliverables and schedules.
Experience
Senior Design Engineer
Aug 2025 — Present · Bengaluru, IN
Bengaluru, Karnataka, India
Education
Bundelkhand University
Bachelor of Technology (B.Tech.)
2010 — 2014
Bundelkhand University, Jhansi
Bachelor of Technology (B.Tech.)
2010 — 2014
Skills
- Standard Cell
- Microsoft Office
- Sales
- Design Rule Checking (Drc)
- Leadership
- Microsoft Word
- Management
- Research
- Physical Verification
- Powerpoint
- Microsoft Excel
- Layout Versus Schematic (Lvs)
- Training
- Photoshop
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