Robin Garg
DV, UPF, Methodology, AI/ML Silicon
- Role
- Principal Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Robin Garg
Robin specialises in Functional Verification, Power Aware Design Verification, UPF Design, and DV Left Shift TFMs. He has extensive hands-on experience working with teams/stakeholders across the globe and has successfully lead (first pass Silicon) end-to-end product verification lifecycle at Subsystems and SoC levels for multiple generations of Server, Client Graphics, Mobile, and IoT products.Presently working as GPU DV Architect at Intel, he has previously worked on NUVIA SoCs, Oryon CPUs, ARM Subsystems, and Qualcomm Modem/Mobile SoCs. As an early employee at NUVIA (now Qualcomm), he worked across DV, TFM, EDA, Design; built functional and Low Power Design/DV infrastructure ground up at IP, SS, and SoC levels; and was instrumental in developing multiple left shift methodologies. Robin is a respected voice in the semiconductor industry. He is a published Author (bestseller book), and Instructor of multiple courses (among Top 3% worldwide). He is a Steering Committee Member for DVCON India and has multiple Technical Paper and Poster Presentations spanning across DV. Views expressed on this platform are Robin’s personal views and not of his employer!
Experience
Principal Engineer
May 2024 — Present
Building best-in-class end to end DV engineering solutions and teams.
Education
Birla Institute of Technology and Science, Pilani
B.E.(Hons), Electrical and Electronics Engineering
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