Robert Wagner
Physical Design Engineer - SoC Physical Integration/Layout
- Role
- Physical Design Engineer at Intel
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Robert Wagner
SoC Physical Integration/Layout Engineer with extensive experience defining and implementing full chip floorplans, chip construction methodologies, physical/layout design verification and Mask Shop entry for multibillion transistor designs across multiple processes shrink nodes and Foundries. Senior Layout designer with strong background in both Digital and Analog designs.
Experience
Physical Design Engineer
Jan 2013 — Present
Skills
- Calibre
- Drc
- Lvs
- Analog
- Physical Design
- Floorplanning
- Soc
- Pll
- Physical Verification
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