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Robert Lipsey

Fellow at Cadence Design Systems

Role
Fellow at Cadence
Location
Fort Collins, CO, US
LinkedIn followers
500 followers
Information TechnologyView LinkedIn profile

About Robert Lipsey

Over 16 years experience in ASIC physical design. Expert in high performance / lower…

Experience

  1. Fellow

    Cadence

    Jul 2015 — Present

Education

  • University of Virginia

    Bachelor of Science (B.S.)

    1991 — 1995

  • University of Virginia

    Master of Science (MS)

    1995 — 1997

Skills

  • Low-Power Design
  • Arm
  • Asic
  • Tcl
  • Eda
  • Clock Tree Synthesis
  • Timing Closure
  • Cadence Encounter
  • Static Timing Analysis
  • Physical Design

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Robert Lipsey — Fellow at Cadence in Fort Collins, CO, US | Unifers