Robert Landy

Experience

1. Cad Engineer

   AMD

   Oct 2019 — Present · San Jose, CA, US

Education

• University of South Carolina

  BS, Electrical Engineering

  1982 — 1986

Skills

• Drc
• Verilog
• Low-Power Design
• Static Timing Analysis
• Lvs
• Ic
• Physical Design
• Tcl
• Eda
• Logic Design
• Cmos
• Soc
• Timing Closure
• Functional Verification
• Primetime
• System on a Chip (Soc)
• Asic
• Integrated Circuit Design
• Systemverilog
• Application-Specific Integrated Circuits (Asic)
• Physical Verification
• Vlsi