Rajesh Kumar Reddy T.

About Rajesh Kumar Reddy T.

Hi, I\'m Rajesh Kumar Reddy Tadi, a master\'s student in computer engineering specializing in VLSI/SOC Design and Design Verification. With expertise in Cadence Virtuoso, Synopsys Design Compiler, and Verilog, I\'ve led projects optimizing chip performance and efficiency. From reducing parasitic effects by 15% to crafting efficient hardware accelerators for machine learning, I\'m eager to bring my skills to roles in Physical/SOC Design and Design Verification/Testing. Let\'s connect to discuss how I can contribute to your team\'s success. Proficient in: Floor Planning Analyzing Congestion during Placement Clock Tree Synthesis Static Timing Analysis Custom Routing Power Analysis and Optimization Timing DRC Fixes Setup and Hold Time Optimization Tools I\'m Familiar with: Cadence Virtuoso Innovus Synopsys Design Compiler HSPICE ModelSim Calibre (DRC, LVS, Pex) MATLAB Simulink IC Validator (Layout)

Experience

1. Electrical Engineer (Component Library)

   Vertiv

   May 2025 — Present · Columbus, OH, US