Riyaz Mohammad
Design Verification Engineer| Gate Level Simulation (GLS) |Capgemini Engineering
- Role
- Professional ll at Capgemini Engineering
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Riyaz Mohammad
Worked on - UPF - GLS setup, SOC level verification - Low power Verification (PG)- Timing simulations (SDF)- Familiar with python scripting- XPROP sim- UVM-HDL Modeling and UVM Simulation Tools: Synopsys vcs, Verdi, cadenceSKILLS->Verilog Programming->System Verilog->Assertion Based System verilog->Universal Verification Methodolgy.
Experience
Professional ll
Oct 2025 — Present · Bengaluru, IN
Education
Jayamukhi Institute of Technological Sciences
Bachelor of Technology - BTech
2016 — 2019
State Board of Technical Education and Training
High School Diploma
2013 — 2016
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