Riya Tyagi

About Riya Tyagi

As a Staff Physical Verification Engineer with over 6+ years of experience in advanced nodes (<N5), I specialize in delivering end-to-end signoff for complex SoCs — ensuring designs are robust, manufacturable, and on-time.My expertise spans DRC/LVS/ANT/PERC, 3D-IC physical verification and signoff flow automation using Tcl and Shell scripting. I’ve successfully led 7+ full-chip tapeouts, collaborating closely with PD, CAD, and foundry teams to achieve clean-by-construction design closure across TSMC, Intel, and Samsung technologies.At Synopsys and Cadence, I’ve contributed to flow optimization and tool validation, including implementing an Oasis-based signoff flow that improved runtime by 80%. I thrive on solving complex verification challenges, building efficient methodologies, and mentoring new teammates making every tapeout smoother, faster, and smarter.

Experience

1. Staff Solutions Engineer - Physical Verification

   新思科技股份有限公司

   Feb 2025 — Present · Hyderabad, IN

   Working in the Test Chip Implementation team, integrating Silicon Lifecycle Management(SLM) IPs on advanced technology nodes (<N5).• Successfully completed 7 full-chip tapeouts, leading 4 of them end-to-end from datapreparation to foundry signoff.• Executing SoC and block-level signoff checks including DRC, LVS, ERC, Antenna, LUP, ESD,and PERC for multiple foundries (TSMC, Intel, Samsung).• Managing end-to-end Physical Verification flow — from GDS generation, fill insertion, toPV signoff and waiver documentation.• Worked on 3D-IC projects, handling advanced stacked die integration verification.• Conducted Layout vs Layout (LVL) and Package LVS closure checks to ensure top-leveldatabase consistency.• Performed RDL (Redistribution Layer) routing for bumps and ensured compliance withsignoff rules.• Implemented Oasis-based Signoff flow, migrating from GDS-based flow and improvingruntime efficiency by 80% through optimized data handling and automation.• Write and maintain Tcl scripts to automate PV tasks, generate reports, and implement fixesfor design rule violations.• Collaborate with Physical Design teams for floorplan, macro placement, bump assignment,and ESD planning to achieve clean-by-construction results.• Work with CAD teams to optimize PV flows and improve runtime efficiency across processnodes.• Mentored new engineers on PV flows, debug methodologies, and signoff best practices.• Proficient in Unix, Shell, and Tcl scripting for automation and flow improvement.