Ritul Shah
- Role
- Astera Labs
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Ritul Shah
HVLs: Systemverilog, C++, Verilog.# EDA tools: VCS, debussy, verdi, IUS, Simvision,…
Experience
Present
Education
Hemchandracharya North Gujarat University
BE in Electronicas & Communication, VLSI
2003 — 2007
Skills
- Asic Verification
- Pcie
- Open Verification Methodology
- Fpga
- Debugging
- Asic
- Perl
- Eda
- Systemverilog
- C++
- Testing
- Verilog
- Functional Verification
- Vlsi
- Simulations
- Application-Specific Integrated Circuits (Asic)
- Pci-Express Gen3
- Vcs
- Ovm
- Ncsim
- Soc
- Veritas Cluster Server
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