Rishikesh K
AMS Verification Engineer @ cadence design systems
- Role
- Design Engineer i at Cadence
- Location
- Madurai, TN, IN
- LinkedIn followers
- 500 followers
About Rishikesh K
AMS Verification Engineer at Cadence Design Systems,with expertise in Verilog-AMS (electrical and Wreal modelling), System Verilog RealNumber Modelling (SV-RNM real and EEnet), connect modules and co-simulation. working in DDR, LPDDR and GDDR PHYs. Skilled in developingand verifying mixed-signal models, with a solid foundation in utilizing the CadenceXcelium and spectre simulator.
Experience
Design Engineer i
Aug 2025 — Present · Bengaluru, IN
AMS Verification | SSG MIG PHY | Woring on DDR5 and LPDDR6 PHY projects on tsmc n2p(2nm),n3p(3nm), 5nm and Samsung SF4X
Education
St.John's matric Hr.Sec School
Higher Secondary
KLN College of Engineering, Madurai, India
Bachelor of Engineering - BE, Electronics and communication Engineering
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