Rishabh Bhargav
Design Verification Engineer at Google
- Role
- Design Verification Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Rishabh Bhargav
Design verification (SoC DV, IP DV): Expertise in creation of verification plan, test bench development, generation of constrained random stimuli, feature verification and debug, functional and code coverage analysis/closure.• Formal Verification: Expertise in doing SoC checks/IP verification using formal techniques• Programming Languages: C/HDL (Verilog)• Scripting languages: Perl, TCL• Tools: NCSIM, IEV, JG (FPV, CSR), vManager, vPlanner
Experience
Design Verification Engineer
Apr 2021 — Present · Bengaluru, IN
Design Verification at IP and Subsystem level designs
Education
National Institute of Technology Srinagar
B.Tech, Electrical, Electronics and Communications Engineering
2011 — 2015
Birla Institute of Technology and Science, Pilani
Master of Engineering (M.Eng.), Microelectronics Engineering
2016 — 2018
Skills
- Microsoft Office
- Matlab
- Engineering
- Proteus
- Powerpoint
- Robotics
- Embedded Systems
- Pspice
- Rfid Applications
- Embedded C
- Pic Assembly
- Vhdl
- Digital Electronics
- C
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