Rishabh Bansal

About Rishabh Bansal

I am working as Staff Analog Layout Engineer. I am having 12+ years of experience in the Analog Layout domain and 14+ years experience as a whole. I have worked on different analog modules such as Differential Pair, Current Mirror, Cascade & Cascode Mirror, Amplifier, Comparator, Bias Generator, Bandgap Reference (BGR), PLL, VCO, Charge Pump, Ring Oscillator, Level Shifter, Regulator, Rectifier, Low Drop Out (LDO) Regulator, Delay Locked Loop (DLL), Booster Monitor, Receiver IP etc. While designing all the blocks Antenna, EM, IR Drop, ESD, Matching, Shielding, STI, Well Proximity, DFM issues, Latchup, DRC, ERC rules have been taken into consideration. For verification I have used Assura, Calibre, Hercules VUE DRC & LVS. I have worked on TSMC 22nm, 28nm, 40nm, 45nm, 65nm, 90nm, 180nm, 250nm, GF 55nm, 130nm and Aptina 13 (130nm) technologies. I also have basic knowledge of Cadence Skill and Perl Scripts. I have been associated with individual IP level responsibilities from block to top level too. I have been involved in both chip level and IP level deliveries and tapeouts with leading and managing the team in previous and current job roles.Specialties: Layout Design, Cadence 6.1.7 (Virtuso, Assura, Calibre), Mentor Graphics (Pyxis, Calibre), Synopsys Herculues VUE, Silvaco 4.8.30 (Gateway, Expert, Gaurdian DRC/LVS), Tanner 13.02(Sedit, Ledit, DRC, LVS, Tspice), Xilinx 14.1, Modelsim 10.1, OrCAD, MATLAB, Simulink, VERILOG/VHDL, Analog & Digital VLSI Design.

Experience

1. Staff Layout Engineer

   onsemi

   Aug 2024 — Present · Bengaluru, IN

Education

• The ICFAI University, Dehradun

  Bachelor's degree

  2007 — 2011