Ridwanallah Giwa

Logic Soc Design Engineer @Intel

Vancouver, BC, CA

Collaborate with IP providers to integrate and validate IPs, ensuring smooth pre-silicon IP-SoC handoff.Develop SoC logic design, register transfer level (RTL) coding, and simulation, integrating IP blocks and subsystems into full chip or discrete component designs.Performing CDC and RDC verification for complex SoC designs, identifying and resolving metastability and glitch issues to ensure reliable data transfer across multiple clock domains.

Obafemi Awolowo University

Pre-Degree

The University of Texas at Dallas

Bachelor's degree

University of Waterloo

Master's degree

Olashore International School

WAEC , IGCSE