Ridhi Tiwari

About Ridhi Tiwari

Completed my M.Tech in VLSI design from Delhi. And actively looking for career opportunities in digital VLSI design. Interested in working as a design/verification engineer in digital VLSI design domain.Can join immediately in one month. Areas of Interest: Digital VLSI Design VLSI Design Flow (RTL-GDS) Memory Design and Testing Digital Hardware Design(RTL, & FPGA)Skills, tools and tech:Verilog, cadence virtuoso schematic, and layout editors, Xilinx vivado, ELDO(basics)RTL-GDSII tools: NCSim, Incisive, RTLCompiler, Tempus, EncounterCurrently, I\'m working on L1-L2 cache sub-system design (a memory design project underSTMicroelectronics mentorship)with a team size of 11The project aims at reducing the dynamic power consumption of the memory compiler by 50%. Pre-layout simulations have shown good amount of power gain, layout is ongoing. Post layout integration would be done by integrating the designed architecture with the STMicroelectronics compiler.

Experience

1. Senior Engineer, Physical Design

   Renesas Electronics

   Jun 2025 — Present · Noida, IN

Education

• IIIT Delhi

  M.TECH, VLSI and Embedded syatem

  2019 — 2021

• Raj Kumar Goel Institute of Technology, Ghaziabad

  Bachelor of Technology, Electronics and communication engg

  2014 — 2018