Riddhi Kapasi
- Role
- Sr Fpga Asic Design Verification Engineer at SpaceX
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Riddhi Kapasi
I have 10* years of experience in ASIC field, mainly in design verification of complex…
Experience
Sr Fpga Asic Design Verification Engineer
Dec 2021 — Present
Working towards bug free ASICs that goes in the Satellites, Gateway terminals and User terminals for the Starlink internet constellations, enabling satellite internet access across multiple countries.
Skills
- Simulations
- Perl
- Application-Specific Integrated Circuits (Asic)
- Testing
- Debugging
- Uvm
- C++
- Dft
- Very-Large-Scale Integration (Vlsi)
- Oop
- Systemverilog
- Verilog
- Rtl Verification
- Asic
- Tcl
- Hardware
- Vlsi
- Vhdl
- C
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