Richard Ho

About Richard Ho

Dynamic and innovative leader with a track record of building teams, creating solutions to hard problems and getting things done. A hands-on leader who executes and implements in addition to planning and managing. Some highlights of impact- Leading Hardware team at OpenAI - Twice published in Nature on photonic AI compute chip and use of ML for chip design - Taped out world\'s first photonic compute chip capable of running full ML - NeurIPS poster on use of graph neural-networks to predict verification effectiveness - Nature-published research into using ML for chip design (macro placement)- The original ML Accelerator (Tensor Processing Unit) that re-ignited computer architecture innovation- The first low-power Arm SoC for data center applications- The Anton1 and Anton2 machines, which both won the Gordon Bell Prize for Computer Architecture- Key technology development of Clock-Domain Crossing (CDC) verification methodology- Mainstream adoption of formal verification for hardware design- Industry adoption of Assertion-Based Verification for hardware design including SVA definition- Co-founded EDA company bought by Mentor Graphics/Siemens - still available as part of Questa Suite. Specialties: ML system design and implementation including SoC and ASIC design, verification and implementation and full system management/execution. Special focus on - Advanced packaging - Heterogeneous integration - High speed, high bandwidth IO networking - Advanced memory With deep knowledge of computer architecture, ML acceleration, advanced chip design analysis techniques that include formal verification (model checking), assertion-based verification, coverage-driven verification and specialized methods such as clock-domain crossing analysis. I aim to build teams that efficiently build novel chips attacking the hardest problems with creativity and flair. Publications: bit.ly/RichardHoGoogleScholar As of March 2025 - 42 patents covering design automation, ML for chip design and photonics (see below). Work using ML for chip design published in Nature:

Experience

1. Head of Hardware

   OpenAI

   Nov 2023 — Present · San Francisco, CA, US

Education

• UCLA Anderson School of Management Extension

  Technical Management Program

  2001

• Stanford University

  Ph.D, Computer Science

  1990 — 1996

• The University of Manchester

  M.Eng, B.Sc (Hons), Microelectronic Systems Engineering

  1986 — 1990

Skills

• Debugging
• Functional Verification
• Eda
• Soc
• Asic
• Computer Science
• Computer Architecture
• System on a Chip (Soc)
• Tcl
• Python
• Simulations
• Xilinx
• C
• Systemverilog
• Formal Verification
• High Performance Computing
• Vlsi
• Rtl Design
• Processors
• Arm
• Application-Specific Integrated Circuits (Asic)
• Perl
• Microprocessors
• Verilog
• Algorithms