Richa Pandey

About Richa Pandey

Hello! I am Richa Pandey, an accomplished VLSI Design and Verification Engineer with a passion for driving innovation in semiconductor verification. With hands-on experience in SoC-level functional verification, I specialize in UVM testbench development and the RTL-to-GDSII design flow. My expertise in SystemVerilog, UVM, and AMBA protocols allows me to deliver high-quality, silicon-ready solutions within stringent timelines. I thrive in collaborative environments, leveraging my analytical acumen and methodical execution to achieve successful verification outcomes. Throughout my career, I have built complete verification environments from scratch, ensuring robust functional coverage and compliance with complex SoC specifications. I am skilled in debugging, regression testing, and coverage closure using advanced tools, which has significantly reduced verification cycles. My commitment to excellence is reflected in my ability to manage low-power verification workflows and optimize design efficiency. Key Achievements- Developed a scalable verification environment that improved modularity and reduced setup time for new SoC programs by 30%- Achieved a significant reduction in pre-silicon defects through proactive regression planning and efficient defect triage mechanisms- Successfully verified two complex automotive SoC integrations end-to-end, ensuring stability and protocol compliance across subsystems.

Experience

1. Senior Hardware Engineer

   Samsung Semiconductor

   Aug 2022 — Present · Bengaluru, IN

   In my role at Samsung Semiconductor, I led SoC-level functional verification for automotive chipsets, establishing UVM-based verification environments from scratch. I developed and maintained comprehensive testbench architectures, ensuring end-to-end functional validation. My responsibilities included executing verification planning derived from design specifications and managing low-power verification workflows. I collaborated closely with cross-functional teams to optimize verification processes and reduce debug cycles across multiple IP integrations.Achievements: I successfully built a scalable verification environment that improved modularity and reduced setup time for new SoC programs by 30%. My proactive regression planning led to a significant reduction in pre-silicon defects, and I verified two complex automotive SoC integrations end-to-end, ensuring stability and compliance across subsystems. My efforts resulted in measurable improvements in verification turnaround time and regression coverage efficiency.

Education

• B S S Public School

  Intermediate

  2013 — 2014

• FEROZE GANDHI INSTITUTE OF ENGG AND TECHNOLOGY , RAEBARELI

  B.Tech, Electronic & Communication Engineering

  2014 — 2018

• Banasthali Vidyapith

  M.Tech , VLSI Design

  2020 — 2022

• Lucknow Public School, Lucknow

  High school

  2011 — 2012