Rich Zimering
Principal Engineer at Marvell Technology
- Role
- Principal Engineer, Asic Physical Design at Marvell Technology
- Location
- Palo Alto, CA, US
- LinkedIn followers
- 500 followers
About Rich Zimering
25+ years experience in IC design: Custom circuit design, full-chip STA, Verilog-to-GDS2 PD, low-skew clock mesh design and optimization, MC Spice simulation, early timing flow, power integrity, dynamic power consumption analysis, Verilog RTL coding, engineering management.
Experience
Principal Engineer, Asic Physical Design
Oct 2021 — Present · Santa Clara, CA, US
Fullchip clock mesh implementation and analysis for TeraLynx10 5nm switch silicon chip, using ICC2, Innovus, Hspice, Primesim, XA, StarRC, QRC. Wrote ICC2 tcl code for clock station and mesh spine analysis simulations in Primesim, Finesim, Hspice, and XA. Use of SunGrid for distributed processing. Measured clock jitter due to DC/AC noise on power rails of a fullchip clock tree.Marvell acquired Innovium in October 2021 for $1.3B in MRVL stock.
Education
Duke University
BSE, Electrical Engineering & Physics
1991 — 1995
University of Cambridge
M.Phil coursework, Microelectronic Engineering and Semiconductor Physics
1995 — 1996
Upper Arlington High School
Diploma, Valedictorian
1987 — 1991
Stanford University School of Engineering
MS coursework (fulltime, onsite for 3 quarters), Electrical Engineering
1997 — 1998
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