Reza Bahadur

Staff Ic Design Engineer @Intel

Fremont, CA, US
MOBILE NUMBERS
+15•••••••83

Signup · Get unlimited contacts

WORK HISTORY

Sep 2015 — Present

Staff Ic Design Engineer @Intel

View department →

Santa Clara, US

Analog Designer in Silicon Photonics Solutions GroupDesign : TIA chip : TIA front end, AGC, Driver for 112 GBPS and 224 GBPS PAM4 OpticalChannel Interface[ 90 nm BICMOS GF 9HP process ]Worked on TIA Design for 112Gbps & 224Gbps PAM4 data. Input PD current 100uA-pp-2.5mA-pp (Optical power -10dBm to 4dBm), Peak-to-Peak Output of 400mV, Gain ranges from 44dB-72dB.Designed output open drain driver to achieve -15dB return loss at Nyquist, for each data rate.• 40 nm – Analog Technical Lead - Design : PMIC – High power current DAC : 14 bit current DACs, 10 bit current DACs - high power.Entire design cycle: chip Architected chip size from scratch, Architected circuit architecture, bump assignment and allocation, floorplanning, Design of analog circuits (65% of SoC). Novel architecture. Integration with digital - in SoC.• BiCmos – 9HP process – Analog Technical Lead - Design : Common Lane for TIA chip : 12 bit ADC, RC oscillator, VBG, VTOI, AMUX, ESDs, VLDOs, POR blocks.Entire Design Cycle (analog circuit design, layout, RV, TOTEM, REL, wafer sort, char, pcb dev, integration into system/product). • 40 nm – Design : SERDES Stand-Alone TX IC Driver. 32 GBPS: CTLE, Limiting Amplifier, Modulator Driver. Designed complete standalone IC TX Driver, to drive Modulator to Modulate Laser light source for High Speed Optical Comm System. Full in-depth study of architecture and interaction between Silicon and Photonics components. • 45 nm – Design : 6 bit ADC design – 1 GBPS – 3 Stage Pipeline ADC with single stage current based residue generation. Designed ADC with 3 pipeline stages. • 40 nm – Technical Lead – 28 GBPS CDRo Design: CDR Output Driver Improvemento Validation: Lead validation effort to debug previous revision of CDR to diagnose design issue and implement fix.o Characterization: Directed measurement of silicon for multiple protocols.o Wafer Level Testing: wafer level tests, test limits, and analyzing data to optimize yields.

EDUCATION

2009 — 2012

University of California, Davis

MS, Electrical Engineering

2005 — 2009

University of California, Berkeley

BS, Electrical Engineering and Computer Science

SKILLS

Bda CockpitRficFpgaRtl CodingRfMonte CarloVerilogSimulationsAnalog DesignSbrFinfetRtl DesignIntegrated Circuit DesignRtl VerificationElectrical EngineeringTri-GateCscopeCadence SpectreMixed SignalCircuit DesignAnalogLayoutSpiceSynopsis Totem Em/Ir SimulatorMonte Carlo SimulationCadence Virtuoso XlCadence VirtuosoLogisimRf DesignCmosIntegrated Circuits (Ic)Analog Circuit DesignC++Cst Microwave StudioAdeCadenceIcSemiconductorsSynopsis Sbr Titan Oa Auto RouterProtel

ABOUT REZA BAHADUR

Specialties: Analog Design, IC Design, RF DesignBS EECS Berkeley, MS EECS Davis.US citizen

This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.