Revati Chavan
Analog Layout Design Engineer 1 at Cadence Design Systems
- Role
- Design Engineer i at Cadence
- Location
- Kolhapur, MH, IN
- LinkedIn followers
- 500 followers
About Revati Chavan
Hands-on experience in FinFET technology for advanced nodes (3nm, 5nm, 7nm) and Planar technology for 28nm.Good knowledge of analog layout techniques which includes Parasitic matching, Device Matching, Well- proximity effect, LOD, Shielding, Minimizing parasitic capacitance.Good understanding in reliability issues like Electromigration, Latch-up.Experience with Layout verification activities like DRC, LVS, EMIR.Good understanding of Analog Circuit Design Basics and Fabrication processes and their effects on layout.
Experience
Design Engineer i
Jul 2025 — Present · Bengaluru, IN
Education
N M A M Institute of Technology, NITTE
Bachelor of Engineering - BE
2020 — 2024
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