Venkata Sai Revanth Kadiri

About Venkata Sai Revanth Kadiri

I am a Graduate Teaching Assistant and a Graduate Service Assistant at Arizona State University, where I am pursuing my Master of Science in Electrical and Electronics Engineering with a specialization in Electronic and Mixed-Signal Circuit Design. My passion is to explore and innovate in the world of VLSI design and semiconductor technology, and to apply my knowledge and skills to create efficient and cutting-edge solutions for challenging projects in this field. I have hands-on experience in RTL-to-GDS2 ASIC design, using tools like Cadence and Synopsys, and coding in Verilog, which I can practically speak fluently. I have also worked on projects such as speeding up Graph Convolution Networks and optimizing 6T SRAM for noise margins. Additionally, I have earned multiple certifications in VLSI design flow, computer architecture, and accelerated AI, and maintained a 3.98/4.0 CGPA in my academic journey. At Honeywell Connected Enterprise, I enhanced a web application with Java, Oracle-SQL, and Jasper reports, and integrated new services into the Honeywell webpage. I am eager to learn from and contribute to the professional world of VLSI design and semiconductor technology. I am actively seeking Spring 2024 Co-op and Full-Time opportunities that allow me to leverage my skills and interests, and collaborate with talented and diverse teams. I believe that every day is a chance to learn something new and make a positive impact.

Experience

1. Asic Design Engineer

   Western Semiconductor

   Feb 2025 — Present

   Implemented bimodal Branch Prediction Unit (BHT/BTB) RTL from scratch in Verilog for an embedded-class RISC-V CPU subsystem at 7nm, then drove the complete RTL-to-GDSII flow including synthesis (DC), floorplan, SRAM macro placement, CTS, routing, and timing closure at 1 GHz; currently supporting physical implementation of the L1 Instruction Cache block focusing on SRAM macro integration and congestion management.• Performed post-route power analysis using PrimeTime PX, annotating SAIF-based switching activity from gate-level simulation to quantify dynamic power from high-toggle BHT counters and leakage from BTB SRAM arrays; flagged per-hierarchy hotspots to support RTL-level clock gating decisions; assisted in UPF-based isolation and retention cell verification across multi-voltage domains.• Ran STA across 12+ PVT/RC corners, debugging SRAM interface timing on BTB tag-compare and fetch-redirect paths at 7nm; executed timing ECOs (buffer insertion, VT swaps, cell resizing) contributing to WNS improvement from -80ps to +20ps and >95% TNS reduction.• Developed Python and Tcl scripts to automate PT-PX report parsing, switching activity aggregation, and ECO tracking, reducing manual effort by 25%.

Education

• Arizona State University

  Master of Science - MS, Electrical and Electronics Engineering

• Jawaharlal Nehru Technological University

  Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering