Reshav Jaswal

About Reshav Jaswal

I am an M.Tech VLSI Design student at NIT Jalandhar with hands-on industry experience in functional and formal verification.Currently, I am working as a Design & Verification Intern at Infineon Technologies, where I am involved in IP-level verification using SystemVerilog and assertion-based verification (SVA). My work includes FSM verification, protocol compliance checking, and debugging RTL issues using waveform analysis and formal counterexamples with JasperGold.I have practical exposure to verification methodologies and on-chip protocols including AHB, APB, I2C, and I am comfortable working in UNIX/Linux-based development environments.Along with core verification work, I have exposure to GenAI-assisted verification workflows that support faster RTL understanding, efficient debugging, and improved productivity.I am focused on strengthening my fundamentals in digital design and verification through continuous learning and hands-on industry experience.

Experience

1. Design & Verification Intern

   Infineon Technologies

   Jul 2025 — Present · Bengaluru, IN

   Working on functional and formal verification of IP-level blocks using SystemVerilog and assertion-based verification (SVA).Analyzing FSM behavior and control logic to ensure correctness across normal and corner-case scenarios.Verifying protocol compliance for on-chip interfaces such as AHB, APB, I2C.Debugging RTL failures using waveform analysis and formal counterexamples in JasperGold.Collaborating within a UNIX/Linux-based verification environment following industry-standard workflows.

Education

• Dr. B. R. Ambedkar National Institute of Technology (NIT), Jalandhar

  Master of Technology - MTech

• DAV Public School, Kumarsain, Shimla

  10th

• Him Academy Public School

  12th

• Bennett University

  Bachelor of Technology - BTech