Renu Rawat

Principal Memory Design Engineer | IIMA

Role
Principal Design Engineer at Cadence
Location
Bengaluru, KA, IN
LinkedIn followers
500 followers

About Renu Rawat

With over 13 years of experience in memory IP design, I specialize in SRAM circuit design and validation, memory architecture, and low-power techniques. My current role as Principal Design Engineer at Cadence builds on my expertise in leading memory compiler design and verification across advanced technology nodes, from 40nm to 2nm. I am committed to fostering collaboration and guiding teams in cutting-edge projects, leveraging my leadership in project planning, cross-site coordination, and mentoring. My work focuses on optimizing memory solutions with a clear emphasis on high-density, low-power, and ultra-high-speed designs, while driving innovation in advanced semiconductor technologies.Main responsibilities :o Full memory compilers platforms and memory flow development.o Solid technical knowledge and expertise in all phases of design and development of memory compilers from specification to tape-out. o Create & review(over time) memory methodologies for compiler.o Identify and highlight potential risks, critical issues in products to senior management with possible aversion or mitigation plans. o Rigorous and comprehensive following of processes and methodologies to ensure high quality deliverables. o Extensive exposure to project planning, scheduling, resourcing and prioritization and tracking of activities during project lifecycle.

Experience

  1. Principal Design Engineer

    Cadence

    Aug 2025 — Present · Bengaluru, IN

    Cadence acquired ARM Artisan Foundation IP business

Education

  • Training

    DRDO

  • Indian Institute of Management Ahmedabad

    Executive MBA

  • G.B. Pant Govt. Engineering College

    Bachelor of Technology (BTech), Electronics and Communication Engineering

    2008 — 2012

Skills

  • Sram Circuit Design & Validations
  • Unix
  • Semiconductors
  • Cadence Virtuoso
  • Microsoft Excel
  • System on a Chip (Soc)
  • Very-Large-Scale Integration (Vlsi)
  • Circuit Design
  • Linux
  • Field-Programmable Gate Arrays (Fpga)
  • Circuit Analysis
  • C
  • Vlsi
  • Soc
  • Debugging
  • Silicon
  • Cmos
  • Integrated Circuits (Ic)
  • Vhdl
  • Spice
  • Perl
  • Eda
  • Matlab
  • Low-Power Design
  • Scripts
  • Vlsi Cad

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Renu Rawat — Principal Design Engineer at Cadence in Bengaluru, KA, IN | Unifers