Reddyrahul Chenga
Principal Engineer at Sandisk
- Role
- Principal Engineer at Sandisk
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Reddyrahul Chenga
FPGA/RTL Design engineer with 8+ years of experience in,FPGA/Emulation Prototyping, SOC IP Integration, RTL/FPGA design and integration using VHDL/Verilog language. OS - Windows/Linux.Good knowledge in git and svn. Designed communication protocols like I2C, SPI, UART, ARINC 429, AXI lite and APB. Have done On Board testing using chipscope, logic analyzer, gologic, USB Lecory analyzer, and IDC toolsWorked on Libero, Vivado, modelsim, VCS, visio, Simvision, HAPS protocompiler, Synplify premier, ncsim, Xecelium.Prototyping Platform: Worked on HAPS70/100 platforms, Palladium XP2/Z1 and Protim S1/X2 emulators.
Experience
Principal Engineer
Feb 2025 — Present · IN
Education
Annamacharya Institute of Technology and Sciences
Bachelor’s Degree, Electrical, Electronics and Communications Engineering
2012 — 2016
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