Razeen Raoof
Gpu Top Level Physical Design Engineer @Apple
Cambridge, GB
EMAILS
MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Mar 2026 — Present
Gpu Top Level Physical Design Engineer @Apple
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Cambridge, GB
EDUCATION
2007 — 2011
RVS CET
Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering
2012 — 2014
Nehru College of Engineering and Research Centre
M.Tech, VLSI
SKILLS
Static Timing AnalysisCHtmlShell ScriptingMicrosoft OfficeMatlabSqlLinuxLayout Versus Schematic (Lvs)Tcl-TkJavaWindowsPowerpointMicrosoft ExcelApplication-Specific Integrated Circuits (Asic)C++Physical DesignPerlEmbedded SystemsDesign Rule Checking (Drc)Microsoft Word
ABOUT RAZEEN RAOOF
Worked on Physical design domain for multiple projects on 3nm, 5nm, 7nm, 10 nm,11 nm and 14nm technologies- Worked on formal verification using Cadence Conformal.* Tools used-Cadence tools: INNOVUS-Synopsys: ICC2,PRIME TIME,Star-Rc.
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