Raviteja Chatta
Staff Engineer @Arm
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WORK HISTORY
Staff Engineer @Arm
Cambridge, GB
Automotive CSS deliverables > Served as technical lead for key Automotive CSS deliverables, including IP-XACT and a RAM integration testbench.> Led a small team across multiple project milestones, contributing directly to implementation while coordinating execution and delivery quality. Ensured alignment with the deliverables quality standards and downstream consumer needs.Microarchitecture of the Debug Subsystem in Automotive CSS.> Made significant contributions to the design of a debug subsystem, with primary responsibility for defining and driving the microarchitecture of the block.> Translated architectural requirements into a robust block-level design, including internal datapaths, control logic and interfaces.> Worked closely with the system architect to influence architectural decisions and ensure alignment between block-level implementation and system-level debug strategy.> Collaborated across RTL and verification teams to deliver a CoreSight-compliant debug solution supporting trace and system observability across multiple clock and power domains.Led the design of an LPDDR5-based memory subsystem > Including ownership of a custom access protection block.> Defined and implemented the subsystem in accordance with performance, security, and debug specifications, balancing throughput, latency, and observability requirements.> Partnered cross-functionally with architecture, RTL, verification and physical design teams to deliver a high-quality subsystems operating across multiple clock and power domains.
EDUCATION
Sree Vidya Niketan ENgineering College, Tirupati
Master's Degree, Digital Electronics and Communication Systems
Rajeev Gandhi Memorial College of Engg. and Tech.
Bachelor's Degree, Electronics and Communication Engineering
Priyadarshini vidya mandir, Dharmavaram
High School, SSC
Narayana Jr. College , Hyderabad
Intermediate, Maths, Physics, Chemistry
SKILLS
ABOUT RAVITEJA CHATTA
I have worked as a SOC/subsystem Integration and verification engineer for nearly 8+ years. My primary focus has always been execution.Worked on various challenging works ranging from subsystem design, optimisation and integration. Verified SOC and subsystem with UVM, SV, and C tests to setting up version control systems and automation of development workflows.Have a good understanding of design and verification environments, C, SV, Python and Perl scripting languages and basic knowledge of UVM.I love to work on challenging tasks.
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