Raviteja Kothuru

About Raviteja Kothuru

15+ years of experience in handling implementation of complex SoC’s across wider technology nodes, ranging from 45nm till 5nm, with major contributions in below work areas - Die Size / Channel Estimations - Pad Planning- Partitioning- Chip Level Integration- Complete PnR / PV and STA closure.• Hands-on experience in implementing Complex Low Power SoC’s involving Multiple Voltage Islands and Power Domains with Isolation, Level shifting and power gating requirements by defining the low power methodology and validate the CPF / UPF for the given low power design specifications. • Capable to drive and work with the cross-functional teams in resolving the issues with respect to Constraint Generation and Validation, Design for Test (DFT), Synthesis, CLP, LEC and IR domains for achieving better QOR and a smoother execution.• Handled designs with complex clock structure at the SoC level, providing solutions for achieving better clock QOR.• Experienced in effectively handling the ECO cycles with critical turn-around times meeting the project schedules. • Good at scripting with TCL / PERL, to automate the requirements at various stages of the Chip Implementation cycle. • Excellent team player and effective in driving the Chip Level PnR interacting with the Block owners in resolving the critical issues upfront. • Self-motivated, adaptive to fast learning with good communication skills. • Familiar with the Industry standard EDA tools for PnR (Cadence EDI / Synopsys ICC / Mentor Olympus), STA (Synopsys PT).

Experience

1. Sr Manager - Ic Design

   Silicon Labs

   Aug 2024 — Present · Hyderabad, IN

Education

• Jawaharlal Nehru Technological University

  Master of Science - MS, VLSI

  2009 — 2011

• Jawaharlal Nehru Technological University

  B.Tech, Electronics and Communications Engineering

  2005 — 2009

• Texas McCombs School of Business

  Postgraduate Programme, AI & ML

Skills

• Tcl
• Low-Power Design
• Logic Synthesis
• Physical Design
• System on a Chip (Soc)
• Perl
• Eda
• Static Timing Analysis