Ravishankar Palagummi
Director, Engineering @ Cisco Systems
- Role
- Director, Engineering at Cisco
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Ravishankar Palagummi
Specialties : SOC/ASIC/FPGA Design, RTL, Micro architecture, Synthesis, Static Timing Analysis, IP Design/Delivery, High Level Synthesis (catapult), Post Silicon Validation
Experience
Director, Engineering
Jun 2025 — Present · San Jose, CA, US
Education
Jawaharlal Nehru Technological University
B.Tech, (Electronics & Communication Engineering)
1998 — 2002
Birla Institute of Technology and Science, Pilani
M.E, (Micro Electronics)
2002 — 2004
Skills
- Fpga
- Asic
- Hardware Architecture
- Soc
- Spyglass
- Logic Synthesis
- Timing Closure
- Data Center
- Fibre Channel
- Functional Verification
- Static Timing Analysis
- Primetime
- Displayport
- Rtl Coding
- Dft
- Formal Verification
- Systemverilog
- Rtl Design
- Integrated Circuits (Ic)
- Vhdl
- Vlsi
- Hdmi
- Specman
- System on a Chip (Soc)
- Ncsim
- Vx1
- Eda
- Verilog
- Ic
- Application-Specific Integrated Circuits (Asic)
- Microarchitecture
- Debugging
- High Level Synthesis
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