Raviraj Kokil

About Raviraj Kokil

10+ years of experience in RTL to GDSII flow across multiple generation of SoC designsHighly skilled in various aspects of IC design such as synthesis, floorplan, placement, UPF & power optimization techniques with deep understanding of clock, route, dfm, timing, logic equivalence, low power checks and other signoff flowsHands on experience with Design Compiler / IC Compiler II / Fusion Compiler across multiple process nodes.

Experience

1. Senior Physical Design Methodology Engineer

   NVIDIA

   Apr 2022 — Present

Education

• Maharashtra Institute of Technology

  BE, E & TC

  2005 — 2009

• Portland State University

  Master of Science (MS), Electrical and Computer Engineering (ECE)

  2013 — 2015

Skills

• Logic Synthesis
• Physical Design
• Synopsys Primetime
• Cadence Virtuoso
• Semiconductors
• Shell Scripting
• Cadence Encounter
• Timing
• Systemverilog
• Atpg
• Linux
• Modelsim
• Microcontrollers
• Signal Integrity
• Functional Verification
• Cadence
• Fpga
• Ic
• Asic
• Tcl
• Debugging
• Timing Closure
• Place
• Dft
• Vhdl
• Simulations
• Formal Verification
• Vlsi
• Verilog
• Primetime
• Place
• Conformal Lec
• Perl
• Embedded Systems
• Eda
• C
• Programming
• Computer Architecture
• Rtl Coding
• Unix