Ravinder Pal Singh Dhanjjal

About Ravinder Pal Singh Dhanjjal

A semiconductor industry (VLSI / chip design) professional with rich experience in managing functional verification (digital verification) of complex system on chips (SoC). The chips range from core-less to multi-core architectures, from general purpose micro-controllers to full custom ASICs and from digital-on-top (mostly digital) to analog-on-top (mostly analog) designs. Target application areas include personal electronics, automotive, network processing and cellular communications.Exposure to various aspects of chip design flow (architecture definition, SoC integration, functional verification, DFT, timing closure, physical implementation, validation and testing).A stint in Intellectual Property (IP) design team has provided familiarity with CPU cores (Power-PC and ARM) and coherent interconnect platforms. Here, also gained experience on IP and sub-system design methodologies and tools.Several years of experience in managing talented local teams and working in close collaboration with teams and management located across geographies, to successfully execute multi-site projects.High technical orientation, with emphasis on quality and attention to detail. Specialties- Front end integration and functional verification of complex multi core system on chips (SoC) and sub-systems (using state of the art C / System Verilog / UVM based methodologies)- People management (including recruiting, mentoring, developing and retaining talent)- Experienced in building and leading mid-size teams.

Experience

1. Senior Group Manager - Digital Verification

   STMicroelectronics

   Dec 2022 — Present

   Heading the team responsible (mainly, but not only) for delivering digital verification of mixed signal ASICs. These ASICs are for applications in personal electronics industry (wireless charging of mobile devices and power management ICs)

Education

• National Institute of Technology Kurukshetra

  B-Tech, Electronics and Communication

  1991 — 1995