Ravikiran Navaratna

About Ravikiran Navaratna

Dynamic, self-motivated and passionate professional with more than 10 years of professional experience in all aspects of ASIC Back-end design, Synthesis & constraint writing.With experience of handling complex block level designs from RTL to GDSII. Including the multi million instances Video cores & Camera blocks & also the high speed ARM CPUs.Exposure of handling the tile flow, with no channels between the blocks, with thousands of feed through within the blocks with Voltage Islands.Specialties : Familiar with the Synthesis & Constraint writingDeep knowledge of ASIC Physical Design flow.Relevant EDA tools exposure for effective execution Static Timing Analysis.Static IR Drop Analysis.Physical Verification.

Experience

1. Principal Engineer

   Marvell Technology

   Oct 2025 — Present · Bangalore Urban, IN

Education

• Infant Jesus School

  SSLC

  2002 — 2004

• Birla Institute of Technology and Science, Pilani

  Master’s Degree, Micro-Electronics

  2013 — 2014

• RV College Of Engineering

  Bachelor of Engineering (BE), Instrumentation Technology

  2006 — 2010

Skills

• Asic
• Pv
• Tcl
• Analog
• Soc
• Floorplanning
• Very-Large-Scale Integration (Vlsi)
• C
• Vhdl
• Application-Specific Integrated Circuits (Asic)
• Physical Verification
• Timing Closure
• Physical Design
• Formal Verification
• Vlsi
• System on a Chip (Soc)
• Drc
• Integrated Circuit Design
• Microprocessors
• Cadence Virtuoso
• Lvs
• Verilog
• Perl
• Embedded Systems
• Eda
• Static Timing Analysis
• Debugging
• Ir Analysis