Ravikiran Murali

About Ravikiran Murali

6+ years of experience in physical design, expertise in high speed clocking GPU clocking architecture and distribution, local clock tree synthesis, UPF compliant clock design Extensive experience on dynamic clock power optimization Latest process technologies, layout design rules aware clock distribution flows FEV checks on the clocking network using Conformal SPICE based simulations using presto and starRC based extraction Clock cell libraries, Clock network integrity and quality Flow development and automation using TCL and PERL on synopsis ICC and ICC2

Experience

1. Senior Graphics Hardware Engineer

   Intel

   Apr 2017 — Present · San Francisco, CA, US

   Tech lead for clocking on Imaging IP. Worked with the RTL/architecture team and clock definition & timing team to understand the various clocks present, their inter-relationships and requirements. Designed, proposed and implemented global clock networks for all the clocks Working with various teams towards improved work efficiency including ICC2 based clock routing tool, design of power-overlay cell for robust power grid connectivity, consolidation of clock flows and tools across teams Developed tcl based scripts for both ICC/ICC2 to automate generation of constraints for FEV checks on clock network due to duplicated logic or pins

Education

• University of Florida

  Master of Science, Electrical and Computer Engineering

  2008 — 2010

• Visvesvaraya National Institute of Technology

  Bachelor of technology, Electronics and Communication Engineering

  2004 — 2008

Skills

• Integrated Circuit Design
• Perl
• Icc2
• Very-Large-Scale Integration (Vlsi)
• Application-Specific Integrated Circuits (Asic)
• Parasitic Extraction
• Static Timing Analysis
• Synopsys Primetime
• Icc
• Layout Verification
• Low Power Design
• Clock Tree Synthesis
• Tcl