Ravikant Acharya
Experienced Physical Design Engineer | Lead Engineer @Cadence | Si-Five | Marvell
- Role
- Lead Pd Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Ravikant Acharya
I\'m an ASIC Physical Design Engineer.
Experience
Lead Pd Engineer
Sep 2024 — Present
Physical Design Engineer | ILM & Hierarchical Flow Specialist | STA, PPA Optimization | 3nm–7nm Nodes | Cadence & Synopsys Tools.PPA push for NPU Cores.Proficient in timing optimization across complex SoC partitions.Tcl/Python automation & signoff methodologies for power, timing, and reliability(EM/IR).
Education
Malaviya National Institute of Technology Jaipur
Master's degree, VLSI
2020 — 2022
Rajasthan Technical University, Kota
Bachelor's degree, Electronics and Communications Engineering
2015 — 2019
GHSS, Shahpura, Bhilwara, Rajasthan
12TH, PCM
2014 — 2015
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