Ravindrareddy Pulicharla
Formal Verification @Meta
- Role
- Formal Verification Engineer at Meta
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Ravindrareddy Pulicharla
Experience in Formal verification, UVM based verification and Functional Safety verification• Expertise on tools like Incisive, Xcelium, IEV, JasperGold, XFS/IFSS(Fault injection tools), IMC and vManager• Good knowledge on Verilog, SV, SVA and UVM• Good academic record - M.Tech from Indian Institute of Technology, Guwahati
Experience
Formal Verification Engineer
Jan 2026 — Present · Bengaluru, IN
Education
Indian Institute of Technology, Guwahati
Master of Technology (M.Tech.), VLSI
2013 — 2015
Hindu Public School, Vinjamur
10th
2005 — 2006
S.V. Junior college, Vinjamur
Intermediate, M.P.C(Maths, Physics, Chemistry)
2006 — 2008
Narayana engineering college, Nellore
Bachelor of Technology (B.Tech.), ECE
2008 — 2012
Skills
- Data Structures
- Field-Programmable Gate Arrays (Fpga)
- C
- Matlab
- Digital Ic Design
- Vlsi Cad
- Latex
- Perl
- System Verilog
- Linux
- Verilog
- Jasper
- Vlsi
- Very-Large-Scale Integration (Vlsi)
- Fpga
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