Ravi Yadav

About Ravi Yadav

As an accomplished SRAM Memory Circuit Design Engineer with over 11 years of experience, I specialize in designing high-density and high-speed memory circuits in FinFET 7-5nm technology. I currently work with Samsung, where I leverage my deep expertise in PPA optimization (power, performance, area), compiler development, and memory circuit design to deliver cutting-edge solutions.Memory Circuit Design and Compiler Development• Design/Implementation/Characterization of various types of Memory Compilers, including SP-SRAM and Multi-Port Register Files (RF).• Proficient in designing Single-Port SRAM and Register Files across multiple process technologies, ensuring robust, high-performance designs.• Marginality Analysis to verify the robustness and performance under process, voltage, and temperature (PVT) variations.• Conducted Parasitic Extraction of Full Memory Cells and Memory Leaf Cells to ensure accurate performance in post-layout scenarios.• Extensive experience in Memory Characterization Flows for critical design aspects such as timing, power, and leakage optimization.• Applied Statistical Analysis to assess and improve memory performance and reliability in different operational conditions.• Deep familiarity with the full-flow methodology for memory compiler design, from feasibility analysis to post-layout validation.• Focused on creating Low-Leakage, High-Performance Memory Compilers, ensuring energy-efficient and high-speed solutions.• Expertise in Low-Power, High-Performance Transistor-Level Circuit Design, implementing advanced techniques to reduce leakage while optimizing speed.• Led Architecture Evaluation for SRAM Compilers and Register Files, identifying the best design approaches to balance performance and power consumption.• Experienced in Design and Analysis of various Memory/SRAM Blocks, ensuring all blocks meet strict performance and design criteria.• Implemented Multi-VT (Threshold Voltage) techniques to enhance speed while minimizing leakage in memory designs.Specialties: Memory Compiler, Design Debug, Characterization,Nanotime, Solido, Bit-Cell Characterization, Monte-Carlo Analysis, Mini-Array, Extraction, Layout Design, Schematic Entry, Physical Verification.

Experience

1. Senior Staff Engineer

   Samsung Electronics

   Dec 2021 — Present · Bangalore, IN

   Successfully delivered 3nm RA1HS Test chip and complier.• Successfully delivered 4nm RA1HS Test chip and compiler with Light sleep feature to save leakage using diode header.• Currently leading the development of the 4nm RA1HS compiler for LVT and RVT designs, focusing on features like leakage-saving mode, pipeline features, BIST for at-speed memory testing, scan chain for control inputs, and reconfigurable registers for col-redundancy.• Responsible for design margin closure, characterization, accuracy checks, PPA, and design closure QA.• Expertise in NANOTIME tool for transistor-level STA analysis, signal integrity, race condition resolution due to process variation, and running custom instance characterizations (LVF, CCS Timing, CCS Noise models).

Education

• Birla Institute of Technology and Science, Pilani

  Master of Technology - MTech, Microelectronics

• Dronacharya Group of Institutions Greater Noida

  Bachelor of Technology - BTech, Electronics and Communications Engineering