Ravi Teja Chinthamaneni
Principal Engineer @Micron Technology
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WORK HISTORY
Principal Engineer @Micron Technology
Hyderabad, IN
EDUCATION
VEDA IIT
Diploma, VLSI Logic Design
Prakasam engineering college
Bachelor of Technology (B.Tech.), Electronics and communications engineering
ABOUT RAVI TEJA CHINTHAMANENI
Handled below front end design tasks-> Master and Slave configurations compliance with MIPI D-PHY v1.2 RTL development in Verilog HDL to interface with DSI and CSI controllers-> RTL level LINT checks with Cadence IES tool to resolve potential errors at early design stage-> Clock Domain Crossing checks with Mentor QCDC tool to qualify domain crossing signals-> SDC development and logic synthesis with Cadence RTL Compiler tool in 22FDX and 14LPP technology nodes-> Logic Equivalence Check with Cadence CONFORMAL tool for netlist and RTL to ensure functionality equivalence-> Support for Timing closure with Synopsys Primetime tool at Physical Design end-> Chip validation support for functional and test modes.
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