Ravi Solanki

About Ravi Solanki

Hands on experience in deep sub micron technologies( 10nm, 40nm, 120nm, 130nm,180nm) Process technologies: UMC,TSMC,GF,IHP,8HP,• Strong skills in floor planning, power planning, shielding and matching techniques• Expert in fixing LVS, DRC, Density, DFM and integration check • Expertise in RAPID ESD and perc_ldl_esd convergence • Proficient in Fusion compiler, FEV, Cadence Virtuoso, Mentor Calibre, ICV Validator, and integration flows with scripting expertise (TCL, Shell) for layout automation & productivity improvements.• Experience in fixing timing violations, max cap violations at integration level.• Addressing EM and RV issues from IP till partition level • Hands-on HV layout experience (HV convergence, EM/IR cleanup, GPIO 3.3V, PROM Fuse, Charge Pump), with strong ESD and latch-up awareness.• Leadership experience: Led multiple HIP projects, coordinated teams of 8 – 12 engineers, managed schedules, and mentored junior engineers for on-time, high quality delivery• Proven track record in full custom analog layout from scratch (LDO, Bandgap Reference, Charge Pump, Voltage Detector, Low Pass Filter, GPIO IP, PROM Fuse)• Strong collaboration history with cross-functional teams, and customers to meet tight tapeout schedules.+ Layout Design for various blocks(RX,TX,V2I,PLL,LNA,PA,PPA)+Physical verification (DRC, LVS and PEX) on Calibre,Assura,PVS+Power/ground structure, block placement and layout floor planning+Prevention of latch-up possibilities & notchfree layouts+Creation of PCELL, PROBE STRUCTURES for RF block, Decap,METSLOTS.+Responsible for timely and quality execution of RF layout,Analog layout,Digital layout work assigned.+Involved in continuous interaction with circuit design engineer regarding various changes and challenges in the design of different blocks.+Good understanding of Layout challenges like overcoming high Density and Low density challenges, Antenna violations, Fixed TOP level POLY, OXIDE, METAL Density errors.+Skill coding,BindKeys

Experience

1. Lead Layout Design Engineer

   Intel

   Sep 2021 — Present · IN

Education

• Rajiv Gandhi Prodyogiki Vishwavidyalaya

  Bachelor's degree, Electrical, Electronics and Communications Engineering

  2007 — 2011

• SGSITS INDORE

  Master's Degree, MICROELECTRONICS AND VLSI DESIGN

  2012 — 2014

Skills

• Mixed Signal
• C
• Microsoft Office
• Photoshop
• Editing
• C++
• English
• Analog
• Teaching
• Verilog
• Budgets
• Vhdl
• Strategic Planning
• Public Speaking
• Research
• Negotiation
• Matlab
• Microsoft Word
• Powerpoint
• Microsoft Excel
• Windows
• Cadence Virtuoso
• Systemverilog
• System Verilog
• Layout Design