Ravi Raj

About Ravi Raj

Verification Engineer having expertise with UVM, System Verilog languages while doing functional verification.VLSI Design Engineer having expertise in developing Front End low power designs for DDR/HBM Memory Controllers using Unified Power Format (UPF) language.Have other/prior experiences in :1) SoC Front End Functional Verification team using OVM/UVM methodolgy and verilog/system verilog language.2) Enabling Low power verification environment using UPF 3) Evaluating the performance of CPU+GPU systems on memory subsystem 4) Integrating subIPs into bigger subsystems and SoCSkill Set:VCS simulations tool and Coverage flow, NCSIM, Unix platform, Cadence Virtuoso, Hspice, Cadence IFV, SimpleScalar, Multi2sim, DRAMsim, DVE,VERDI - waveform viewers, VCS-NLP tool for front end UPF.Specializations: Industry Standard AXI, eSDXC/HC, MMC cards protocol Hardware Language: Unified Power Format - standard language, System Verilog, VerilogSoftware Language: C, C++Scripting Language: Shell, Perl

Experience

1. Design Verification Engineer

   NVIDIA

   Apr 2022 — Present

Education

• University of Minnesota

  Master of Science (MS) in Electrical Engineering, VLSI

  2014 — 2015

• Manipal Institute of Technology

  Bachelor of Engineering (B.E.), Electronics and Communications Engineering

  2006 — 2010

Skills

• C
• Cadence Virtuoso
• Matlab
• C++
• Hardware Architecture
• Systemverilog
• Debugging
• Verilog
• Rtl Design
• System on a Chip (Soc)
• Asic
• Pll
• Logic Design
• Soc
• Functional Verification
• Vhdl
• Simulations
• Very-Large-Scale Integration (Vlsi)
• Integrated Circuit Design
• Microprocessors
• Vlsi
• Microcontrollers
• Modelsim
• Computer Architecture
• Application-Specific Integrated Circuits (Asic)
• Semiconductors
• Formal Verification
• Perl