Ravi Chhabra
- Role
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
Experience
Present
Skills
- Low Power Verification
- Vhdl
- Upf
- Debugging
- Gate Level Simulation
- Verilog
- Python
- Low-Power Design
- Arm
- C
- Application-Specific Integrated Circuits (Asic)
- Physical Verification
- Very-Large-Scale Integration (Vlsi)
- Logic Synthesis
- Physical Design
- Soc
- Field-Programmable Gate Arrays (Fpga)
- Rtl Design
- Dft
- Timing Closure
- Power Analysis
- Static Timing Analysis
- Formal Verification
- Signal Integrity
- Clock Tree Synthesis
- Vlsi
- Universal Verification Methodology (Uvm)
- Functional Verification
- Fpga
- Asic
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