Jatheeshan Raveenthiran
Soc Dfx Design Verification Engineer @AMD
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WORK HISTORY
Soc Dfx Design Verification Engineer @AMD
Markham, ON, CA
Responsible for verifiying and validating pre-silicon RTL of System-of-Chips using Design For Test/Validation principles. Created C++ test sequences using Object-Oriented Programming that are run in test-bench environments.Analyzed digital waveforms to ensure correct behavior of chips in pre-silicon design according to industry standards such as JTAG.Created and maintained Perl/Python/Shell/Bash Scripts to develop/optimize new flows in Linux environment.
EDUCATION
Satec @ WA Porter Collegiate Institute
Ontario Secondary School Diploma
McMaster University
Bachelor's of Engineering & Biomedical Engineering, Biomedical Engineering
ABOUT JATHEESHAN RAVEENTHIRAN
Sr. System-On-Chip Design Verification Engineer @ AMD | Electrical and Biomedical Engineering Student | Undergraduate Student Researcher
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