Raveena Khandelwal
SoC Design Engineer at Intel Corporation
- Role
- System-on-chip Design Engineer at Intel
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
About Raveena Khandelwal
Experienced System-on-Chip Design Engineer with a demonstrated history of working in the semiconductors industry. Strong engineering professional with a Master\'s degree focused in Electrical and Computer Engineering from Portland State University.
Experience
System-on-chip Design Engineer
Jul 2019 — Present · Hillsboro, OR, US
Performing all aspects of Physical Design implementation and verification on high-speed design for the next generation of Intel Microprocessors. Primary DE owner for block-level floorplanning, congestion analysis, design feasibility, routability, timing closure, logical equivalence checking, resolving IR drop/EM checks, design health checks, and ECO implementation/verification. In charge of reviewing and driving convergence of full chip Noise and VCLP violations at sub_fc level.
Education
MGM's Jawaharlal Nehru Engineering College
Bachelor’s Degree, Electronics and Telecommunications
2012 — 2016
Portland State University
Master's degree, Electrical and Computer Engineering
2017 — 2019
Skills
- Microsoft Excel
- Powerpoint
- Strategic Planning
- Microsoft Office
- Microsoft Word
- Leadership
- Management
- Project Management
- Research
- Customer Service
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