Rasika Yelure
Verification engineer in qualcomm
- Role
- Sr Lead Engineer at Qualcomm
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About Rasika Yelure
Completed M.TECH in VLSI design from VNIT, Nagpur. Area of Interest: Digital Design, Physical design,Mixed Signal, ASIC, VLSI Design,Formal Verification *Good experience on Cad tools- Cadence Virtuoso, Cadence layout editor,Mentor Graphics Tool-ELDO.*Good understanding of ASIC design flow from RTL to tape out. I have good knowledge of Analog VLSI Design,Physical Design, Digital VLSI Design, VLSI Design Concepts and VHDL, Verilog Programming through various course works in my M.Tech.
Experience
Sr Lead Engineer
Dec 2022 — Present · Bengaluru, IN
Education
Visvesvaraya National Institute of Technology
Bachelor of Technology (BTech), Electronics and Communication Engineering
2010 — 2014
Visvesvaraya National Institute of Technology
Master of Technology - MTech, Vlsi design
2015 — 2017
Visvesvaraya National Institute of Technology
Master of Technology - MTech, VLSI Design
2015 — 2017
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