Rashmi Dhabale

About Rashmi Dhabale

Currently working with Cadence on new cutting edge technologies and emphasis solely on physical design product Innovus at Block level and Chip Top. Handled multiple issues at different hierarchy which includes debugging critical issues from netlist to GDSII.Worked on all aspects of physical design flow including floorplan, powerplan, placement, clock tree synthesis, routing and timing closure. Apart from this I have good knowledge of• CMOS fundamentals, digital circuit design, ASIC design flow.• Physical design and STA concepts like GBA, PBA, CRPR, MCMM, OCV, AOCV.• Perl, TCL and shell scripting. • Worked on tools like Innovus, ICC, Design Compiler, Prime Time, IC Studio, Xilinx ISE 14.2, Questasim, Modelsim.In nutshell, I am always keen to learn new things and looking for a challenging position that makes me utilize my skills and enhance my knowledge.

Experience

1. Senior Engineer

   Qualcomm

   Dec 2023 — Present · Noida, IN

Education

• Indian Institute Of Information Technology Allahabad

  Master of Technology (MTech), Microelectronics, Microelectronics

  2013 — 2015

• Babasaheb Naik College Of Engineering , Pusad.

  Bachelor of Engineering (BE), Electronics and telecommunication Engineering

  2008 — 2012

Skills

• Rtl Design
• Digital Vlsi Design
• Microcontrollers
• Cmos
• C
• Programming
• Application-Specific Integrated Circuits (Asic)
• Microsoft Office
• Vlsi
• C++
• Verilog
• Embedded Systems
• Cadence Virtuoso
• Static Timing Analysis
• Digital Electronics
• Matlab
• Fpga
• Asic
• Microsoft Excel
• Field-Programmable Gate Arrays (Fpga)
• Very-Large-Scale Integration (Vlsi)
• Vhdl
• Simulations
• Analog Vlsi Design
• Electronics
• Linux
• Xilinx Ise