Rashimol Fither

About Rashimol Fither

Expertise in SoC Power Management and Globals ArchitectureExpertise in all phases of ASIC/SOC Arch, DesignInvolved in Scoping and Architecture of Mulitple Spec to GDS ProjectsWorked on Front End Micro Architecture and Design of ASICs in Video and Networking Domains Guided and Mentored Teams in Design, Validation, Timing and DFTInvolved in defining DFT architecture, Guiding team in implementation, Pattern Generation, Verification and Silicon Debug for Many ChipsStrong Skills in Micro Arch, Design and DFTAwareness in Physical design activitiesAwareness of System/Board Architecture ConceptsVLSI Project Management including Design, DFT, verification, STA and PD

Experience

1. Senior Principal Engineer

   Arm

   Feb 2025 — Present · Bengaluru, IN

Education

• National Institute of Technology Calicut

  M.Tech, Digital Systems and Communication Engg

  1998 — 1999

• Mahatma Gandhi University

  B.Tech, Electronics and Communication Engg

  1994 — 1998

Skills

• Fpga
• Asic
• Verilog
• Vhdl
• Soc
• Logic Synthesis
• Rtl Design
• Dft
• Debugging
• Formal Verification
• Vlsi
• Ic