Rao Mahidhara

Principal Engineer @Silanna Semiconductor

San Diego, CA, US

New Product Introductions voltage regulator switches and RF MCM. Advanced MCM assembly technologies (Chip to wire, CuClip and flip chip) to optimize packaging density, performance and cost. Worked with wafer bumping house and assembly contract manufacturers to define and execute process DOEs, develop new technology, new processes, and new products, data analysis, product / package reliability testing of new technology, technology qualification, reliability monitoring, data analysis and summarization and subsequent production ramp, ensure the changes to new product/process meet or exceed the design reliability, verification of on-going production reliability, and determining and correcting the cause of failure of any products that our customers experience for commercial, industrial and/or automotive application. Managed and executed new product introduction (NPI) involving wafer bumping with Cu Pillars including backend wafer processing (RDL) and qualification. Provided strategic solutions and technical leadership to customer quality issues and drive process robustness, production yield improvement and costing reduction. Managed compliance of NPI designs with CMs internal rules. Utilized tools for Problem solving & continuous improvement (e.g, Six Sigma, 8D, DOE). Applied strong program management skills to keep multiple activities with scope, schedule and tracking of the overall program objectives. Experienced in assembly development for very high volume manufacturing. Applied substrate and assembly Packaging process details, risk assessments, FMEAs, and CARs. Performed FA of and field and qualification test failures analysis.

University of California

Doctor of Philosophy (Ph.D.)