Ranjithkumar Gurusamy
Staff Engineer | RTL Design & SoC Architecture (ISO26262 & Low Power)
- Role
- Staff Design Engineer at Renesas Electronics
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Ranjithkumar Gurusamy
RTL Design Engineer with a decade of experience in low-power ASIC development, managing the entire lifecycle from concept to silicon. I have successfully led digital execution for 4 production tapeouts across radar and automotive SoCs in 40nm, 28nm, and 16nm technology nodes. My work includes delivering 5 generations of MMIC and 1 MaxSDR chip. My core expertise lies in defining Functional Safety (ISO26262) compliant architectures, driving UPF low-power methodologies, and translating complex system requirements into robust RTL designs.
Experience
Staff Design Engineer
Nov 2022 — Present · Bengaluru, IN
Lead RTL design and architectural definition for complex automotive and radar ASICs (40nm, 28nm, 16nm). Manage cross-functional alignment across verification, physical design, and systems teams to ensure successful tapeouts.Key Highlights:• Technical Leadership: Directed a 6-member team through critical micro-architectural upgrades for Arm Cortex-M33 subsystems.• Functional Safety & Low Power: Architected ISO26262-compliant FuSa subsystems for a 40nm NFC chip, reducing dynamic power and SRAM area.• SoC Integration: Designed top-level interconnects and hardware security boundaries (Arm TrustZone, MPUs) for a Secure UWB SoC.• Complex Architectures: Defined system-level RAS frameworks for error correction and built high-speed Die-to-Die (D2D) interfaces for radar chip synchronization.
Education
Kumaraguru College of Technology
Bachelor of Engineering (B.E.), Electronics and Communications Engineering
2012 — 2016
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