Ranjith N G
Physical Design Engineer
- Role
- Design Engineer Ii at Qualcomm
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Design Engineer Ii
May 2024 — Present · Bengaluru, IN
Worked on RTL2GDSII HM\'s level implementation in 3nm Technology Node-> Conducted PNR and timing analysis and ensuring optimal performance, power and area trade-offs->ASIC block level physical implementation, i.e Floor Planning, Power Planning, Placement, CTS, Routing, Timing convergence and layout closures->ECO implementation for timing and functional fixes.
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