Ranjith Maddu

About Ranjith Maddu

Experienced Physical Design Engineer with hands-on expertise in advanced technology nodes including 3nm, 4nm, 5nm, 7nm, and 45nm. Proven track record as a Block Lead, managing floorplanning, place and route (PnR), and signoff closure for complex blocks with up to 1.5 million instances and 2MB cache memory. Skilled in clock tree synthesis, clock power optimization, and DCD improvement. Successfully closed timing for critical interfaces at 1.5 GHz. Proficient in tools like Innovus, ICC2, and Primetime, with strong scripting capabilities in TCL and Shell. Adept at handling timing and congestion-critical designs across multiple technology nodes.Black Pepper:I have worked on the sign-off clouser for blocks in TI companySynapse:Worked with multiple clients at Mediatek Singapore and Mediatek Banglore as a Physical Design Engineer, and later transitioned to a Tile Lead role at AMD ODC, where I successfully managed the implementation of 8 tiles in parallel.Einfochips:I joined Einfochips as a fresher and started working on block-level Physical Design for the Faraday client, focusing on Netlist to GDSII implementation on 45nm technology nodes, within a ODC, where I was responsible for handling multiple blocks and subsystems involving complex timing and congestion challenges

Experience

1. Staff Engineer

   Qualcomm

   Sep 2021 — Present · IN

Education

• A.K.R.G Junior college

  HSC, MPC

  2004 — 2006

• Jawaharlal Nehru Technological University Kakinada (JNTUK)

  Bachelor's Degree, Electronics and communication engineering

  2006 — 2010

• Geethanjali Residential Public School

  Secondary School of Education, All subjects

  1994 — 2004

Skills

• Drc
• Asic
• Tcl
• Logic Synthesis
• Physical Verification
• Cadence Virtuoso
• Lvs
• Cadence
• Linux
• Place & Route
• Static Timing Analysis
• Cmos
• Timing Closure
• Soc
• Clock Tree Synthesis
• Vlsi
• Physical Design
• Primetime
• System on a Chip (Soc)
• Routing
• Integrated Circuit Design
• Scripting
• Floorplanning