Ranjit Kumar
STA and Synthesis Engineer
- Role
- Design Engineer (Sta and Synthesis Engineer) at Mirafra Technologies
- Location
- Ranchi, JH, IN
- LinkedIn followers
- 500 followers
About Ranjit Kumar
Done internship in full chip timing from INTEL, duration is of 13 month.Worked on- Block level timing constraints. Block level timing ECO fix. Full ownership of quality timing tool. Worked on tsmc 3nm technology.Workable knowledge of physical design. Tools- Prime Time (SSA/DMSA) Quality Check Tool ( Caliber tool) DC Genus Cadence ( Virtuoso) TCAD LT-SPICE
Experience
Design Engineer (Sta and Synthesis Engineer)
Jul 2024 — Present · Bengaluru, IN
Education
University College of Engineering & Technology (UCET)
B.TECH
2016 — 2020
Malaviya National Institute of Technology Jaipur
M.TECH
2021 — 2023
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