Ranjeeth R K
ASIC Digital Design Engineer at Synopsys
- Role
- Asic Design Engineer at 新思科技股份有限公司
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Ranjeeth R K
Working as Staff Engineer (FPGA), Velodyne Lidar, India.Experience in FPGA, RTL Coding.Programming Language - Verilog, VHDL, C Tools - VIVADO, XILINX SDK
Experience
Asic Design Engineer
Mar 2023 — Present · Bengaluru, IN
Education
ER & DCI Institute of Technology
Master of Technology - MTech, VLSI & EMBEDDED SYSTEMS
2014 — 2016
Sree Chitra Thirunal College of Engineering, Pappanamcode, Thiruvananthapuram
Bachelor of Technology - BTech, Electronics and Communications Engineering
2010 — 2014
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